This application claims benefit of priority under 35USC xc2xa7 119 to Japanese Patent Application No. 2000-126006, filed on Apr. 26, 2000, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit having FETs for use in ICs or switches for ASK (Amplitude Shift Keying) modulation.
2. Related Background Art
If an FET (field-effect transistor) is used as a switch, the amount of signal transmission is preferably large when it is in an ON state, and the amount of signal transmission is preferably small when it is in an OFF state.
There has been provided a conventional circuit for decreasing the amount of signal transmission so that the drain-to-source voltage Vds of an FET is zero when the FET is in an OFF state. In a circuit of this type, it is difficult to suppress the amount of signal transmission to (xe2x88x9210 dB) or more per one stage of FETs due to the influence of the parasitic capacity of the FET.
FIG. 1 is an equivalent circuit diagram of an FET. Using this equivalent circuit, the reason why the amount of signal transmission cannot sufficiently be lowered when the FET is in the OFF state will be described below.
In FIG. 1, when the FET is in the OFF state, the relationship expressed by the following expressions (1) through (4) is established.
Ri, Rg, Rd, Rs less than  less than Rds less than  less than |1/(xcfx89xc2x7Cds)|xe2x80x83xe2x80x83(1)
gm=about 0xe2x80x83xe2x80x83(2)
Cgd=about Cgsxe2x80x83xe2x80x83(3)
Rd less than  less than Rds less than  less than RLxe2x80x83xe2x80x83(4)
From these expressions (1) and (4), signals inputted to a gate terminal are transmitted to a load resistance RL at a quantity depending on a product of Cgd/(Cgd+Cgs) and Rds/(Rds+RL).
Parameters such as Cgd, Cgs and Rds are functions of the drain-to-source voltage Vds of the FET, and the above described product is not zero when Vds=0.
On the other hand, when Vds is not zero, a product of Vc and gm is not zero, so that there is a problem in that the amount of signal transmission is increased by currents caused by the product of Vc and gm.
Even if the relationship expressed by the above described expressions (1) through (4) is satisfied and even if Vds is selected so that the product of Cgd/(Cgd+Cgs) and Rds/(Rds+RL) is minimum, both of gm and Vc are not zero, so that there is a problem in that the amount of signal transmission is increased by currents depending on the product of Vc and gm.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor integrated circuit capable of decreasing the amount of signal transmission when an FET is in an OFF state as small as possible and of improving a variable ratio of the amount of signal transmission.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor integrated circuit comprises: an FET having a gate terminal configured to input a controlled signal and a drain terminal configured to output a signal corresponding to the controlled signal; and an inductor element provided between a source terminal and a ground terminal of the FET, wherein an inductance value of the inductor element is set so that the inductor element resonates in series for a reactance component of a gate-to-source impedance by the controlled signal when a drain voltage of the FET is lower than a source voltage thereof.
According to the present invention, since the inductor element is provided between the source terminal and ground terminal of the FET to cause the inductor element to resonate in series for the reactance component of the gate-to-source impedance when the drain voltage is lower than the source voltage, it is possible to reduce the amount of signal transmission when the FET is in the OFF state, and it is possible to improve the variable ratio of the amount of signal transmission.
By connecting the inductor element to the capacitor element in series between the source terminal and ground terminal of the FET, the dc component to originally flow through the inductor element can be interrupted by the capacitor element, so that it is possible to reduce electric power consumption.